00972nam a22002177a 4500003000400000005001700004040002200021082000800043100004300051245014600094260005600240300003900296440011900335650008000454650002700534650003500561650001000596650004100606650001500647856009200662SNU20140609174359.0  aNPTELcIIT Madras  a004  aKamakoti, V. and Balachandran, Shankar  aCAD for VLSI Design IIb: Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysisc/ V. Kamakoti and Shankar Balachandran  aIIT Madrasb; Indian Institute of Technology Madras  aChapter 10b; 20 p.f, pdf lecture  aNPTEL Lecture Seriesn , Chapter 10p: Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis  aEstimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis  aCAD for VLSI Design II  aComputer Science & Engineering  aNPTEL  aV. Kamakoti and Shankar Balachandran  aIIT Madras  3pdfuhttp://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/pdf/nptel-cad2-10.pdf