00919nam a22002417a 4500 SNU 20140609175148.0 NPTEL IIT Madras 004 Kamakoti, V. and Balachandran, Shankar CAD for VLSI Design II : Logical effort - Optimizing performance / V. Kamakoti and Shankar Balachandran IIT Madras ; Indian Institute of Technology Madras Chapter 19 ; 23 p. , pdf lecture NPTEL Lecture Series , Chapter 19 : Logical Effort and Gain based Synthesis Logical Effort and Gain based Synthesis CAD for VLSI Design II Computer Science & Engineering NPTEL V. Kamakoti and Shankar Balachandran IIT Madras pdf http://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/pdf/nptel-cad2-19.pdf ddc NPTEL 11063 11063 0 0 ddc 0 0 SNUL SNUL 2014-06-05 0 004 NP96 2014-06-05 00:00:00 2014-06-05 NPTEL