00887nam a22002177a 4500003000400000005001700004040002200021082000800043100004300051245011800094260005600212300003900268440009000307650005200397650002700449650003500476650001000511650004100521650001500562856009200577SNU20140609175225.0  aNPTELcIIT Madras  a004  aKamakoti, V. and Balachandran, Shankar  aCAD for VLSI Design IIb: Logical Effort and Gain based Synthesis (Contd)c/ V. Kamakoti and Shankar Balachandran  aIIT Madrasb; Indian Institute of Technology Madras  aChapter 20b; 22 p.c, pdf lecture  aNPTEL Lecture Seriesn, Chapter 20p: Logical Effort and Gain based Synthesis (Contd)  aLogical Effort and Gain based Synthesis (Contd)  aCAD for VLSI Design II  aComputer Science & Engineering  aNPTEL  aV. Kamakoti and Shankar Balachandran  aIIT Madras  3pdfuhttp://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/pdf/nptel-cad2-20.pdf