TY  - BOOK
AU  - Srinivasan, S.
TI  - Digital Circuits and Systems: Logic Minimization Using Karnaugh Maps
CY  - Madras
PB  - Indian Insitiute of Technology
KW  - Digital Circuits and Systems
KW  - Electronics And Communication Engineering
KW  - IIT Madras
KW  - Logic Minimization Using Karnaugh Maps
KW  - NPTEL
KW  - Prof. S. Srinivasan
UR  - http://video.snu.edu.in/index.php?id=4138&cat=Electronics And Communication Engineering&course=Digital Circuits and Systems&url=Phase1_Video/117106086/lec07.mp4
ER  -