TY  - DATA
AU  - "Biswas, Santosh"
AU  - "Deka, Jatindra Kumar"
TI  - Design Verification and Test of Digital VLSI Circuits: "Introduction to HLS: Scheduling, Allocation and Binding Problem"
CY  - Guwahati
PB  - Indian Insitiute of Technology
KW  - "Introduction to HLS: Scheduling, Allocation and Binding Problem"
KW  - "Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
KW  - Computer Science and  Engineering
KW  - Design Verification and Test of Digital VLSI Circuits
KW  - IIT Guwahati
KW  - NPTEL
UR  - http://video.snu.edu.in/index.php?id=7266&cat=Computer Science and  Engineering&course=Design Verification and Test of Digital VLSI Circuits&url=Phase2_Video/106103116/mod02lec01.mp4
ER  -