01092nmm a2200253 a 4500 SNU 20140915195306.0 140911s9999 xx 000 0 und d NPTEL IIT Guwahati "Biswas, Santosh" "Deka, Jatindra Kumar" Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-2 / Jatindra Kumar Deka and Santosh Biswas Guwahati Indian Insitiute of Technology Video Lecture NPTEL Lecture Series Computer Science and Engineering Scheduling Algorithms-2 "Prof. Jatindra Kumar Deka,Dr. Santosh Biswas" Computer Science and Engineering Design Verification and Test of Digital VLSI Circuits IIT Guwahati NPTEL Scheduling Algorithms-2 Video http://video.snu.edu.in/index.php?id=7268&cat=Computer Science and Engineering&course=Design Verification and Test of Digital VLSI Circuits&url=Phase2_Video/106103116/mod02lec03.mp4 ddc NP SNU 33972 33972 0 0 ddc 0 0 SNUL SNUL 2014-09-15 0 2014-09-15 00:00:00 2014-09-15 NP SNU