TY  - BOOK
AU  - Raasi Chenna
AU  - Madhur Upadhayay
TI  - FPGA Simulation Environment for Pen Verification Module
PY  - 0000///May-19
CY  - Shiv Nadar University 
PB  - Electronics and Communication Engineering
KW  - Project Report
UR  - http://dspace.snu.edu.in:8080/jspui/handle/123456789/582
ER  -