<?xml version="1.0" encoding="UTF-8"?>
<record
    xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
    xsi:schemaLocation="http://www.loc.gov/MARC21/slim http://www.loc.gov/standards/marcxml/schema/MARC21slim.xsd"
    xmlns="http://www.loc.gov/MARC21/slim">

  <leader>01465nam a22002177a 4500</leader>
  <controlfield tag="005">20230920123209.0</controlfield>
  <controlfield tag="008">230920b        |||||||| |||| 00| 0 eng d</controlfield>
  <datafield tag="020" ind1=" " ind2=" ">
    <subfield code="a">9781461186298</subfield>
  </datafield>
  <datafield tag="028" ind1=" " ind2=" ">
    <subfield code="a">: Zafaa Book &amp; Distributors</subfield>
    <subfield code="b">: 313/56F, 49A, Anand Nagar, Inderlok, Delhi.</subfield>
    <subfield code="c">: ZBD0148</subfield>
    <subfield code="d">: 15/09/2023</subfield>
  </datafield>
  <datafield tag="082" ind1=" " ind2=" ">
    <subfield code="a">621.395 STA</subfield>
  </datafield>
  <datafield tag="100" ind1=" " ind2=" ">
    <subfield code="a">Stavinov, Evgeni.  </subfield>
  </datafield>
  <datafield tag="245" ind1=" " ind2=" ">
    <subfield code="a">100 power tips for FPGA designers</subfield>
    <subfield code="c">/ Evgeni Stavinov.</subfield>
  </datafield>
  <datafield tag="260" ind1=" " ind2=" ">
    <subfield code="b">: Evgeni Stavinov</subfield>
    <subfield code="c">, 2011.</subfield>
  </datafield>
  <datafield tag="300" ind1=" " ind2=" ">
    <subfield code="a">xii, 453p.</subfield>
    <subfield code="c">: 26cm.</subfield>
  </datafield>
  <datafield tag="365" ind1=" " ind2=" ">
    <subfield code="b">4307</subfield>
  </datafield>
  <datafield tag="520" ind1=" " ind2=" ">
    <subfield code="a">This book is a collection of short articles on various aspects of FPGA design: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, design methodologies, performance, area and power optimizations, RTL coding, IP core selection, and many others. The book is intended for system architects, design engineers, and students who want to improve their FPGA design skills. Both novice and seasoned logic and hardware engineers can find bits of useful information.This book is written by a practicing FPGA logic designer, and contains a lot of illustrations, code examples, and scripts. Rather than providing information applicable to all FPGA vendors, this book edition focuses on Xilinx Virtex-6 and Spartan-6 FPGA families. Code examples are written in Verilog HDL. </subfield>
  </datafield>
  <datafield tag="650" ind1=" " ind2=" ">
    <subfield code="a">Field programmable gate arrays</subfield>
  </datafield>
  <datafield tag="650" ind1=" " ind2=" ">
    <subfield code="a">Field programmable </subfield>
  </datafield>
  <datafield tag="650" ind1=" " ind2=" ">
    <subfield code="a">Design and construction</subfield>
  </datafield>
  <datafield tag="942" ind1=" " ind2=" ">
    <subfield code="c">BOOK</subfield>
  </datafield>
  <datafield tag="999" ind1=" " ind2=" ">
    <subfield code="c">60857</subfield>
    <subfield code="d">60857</subfield>
  </datafield>
  <datafield tag="952" ind1=" " ind2=" ">
    <subfield code="0">0</subfield>
    <subfield code="1">0</subfield>
    <subfield code="2">ddc</subfield>
    <subfield code="4">0</subfield>
    <subfield code="7">1</subfield>
    <subfield code="a">SNUL</subfield>
    <subfield code="b">SNUL</subfield>
    <subfield code="d">2023-09-20</subfield>
    <subfield code="e">Zafaa Books</subfield>
    <subfield code="g">4307.00</subfield>
    <subfield code="l">0</subfield>
    <subfield code="o">621.395 STA</subfield>
    <subfield code="p">29570</subfield>
    <subfield code="r">2023-09-20 00:00:00</subfield>
    <subfield code="w">2023-09-20</subfield>
    <subfield code="y">BOOK</subfield>
  </datafield>
</record>
