TY  - BOOK
AU  - Aditi Sharma
AU  - Under Supervision of Dr. Venkatnarayan Hariharan
TI  - Processor Design: From Specification to Gate- Level Netlist Realization
PY  - 2024///
CY  -  " Shiv Nadar Institution of Eminence"
PB  - "Department of Electrical and Electronic Engineering, School of Engineering"
KW  -  Engineering
KW  - Electrical Engineering
KW  - Electrical and Electronics Engineering
KW  - B.Tech
ER  -