<?xml version="1.0" encoding="UTF-8"?>
<mods xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://www.loc.gov/mods/v3" version="3.1" xsi:schemaLocation="http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-1.xsd">
  <titleInfo>
    <title>Verilog HDL</title>
    <subTitle> : a guide to digital design and synthesis, IEEE 1364-2001 complaint</subTitle>
  </titleInfo>
  <name type="personal">
    <namePart>Palnitkar, Samir</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <name type="personal">
    <namePart>; Goel, Prabhu.</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <name type="personal">
    <namePart>Samir Palnitkar</namePart>
  </name>
  <typeOfResource>text</typeOfResource>
  <originInfo>
    <place>
      <placeTerm type="text">Noida</placeTerm>
    </place>
    <publisher> : Pearson</publisher>
    <dateIssued>, 2022</dateIssued>
    <issuance>monographic</issuance>
  </originInfo>
  <language>
    <languageTerm authority="iso639-2b" type="code">eng</languageTerm>
  </language>
  <physicalDescription>
    <form authority="marcform">print</form>
    <extent>490p. : 24cm.</extent>
  </physicalDescription>
  <note type="statement of responsibility">/ Samir Palnitkar.</note>
  <subject>
    <topic>Verilog</topic>
  </subject>
  <subject>
    <topic>HDL</topic>
  </subject>
  <subject>
    <topic>Degital Design</topic>
  </subject>
  <classification authority="ddc">621.392 PAL</classification>
  <identifier type="isbn">9788177589184</identifier>
  <identifier type="">: Raghav Books Pvt. Ltd. : A-184, A Nand Gram, Ghaziabad, Ghaziabad</identifier>
  <recordInfo>
    <recordCreationDate encoding="marc">241112</recordCreationDate>
    <recordChangeDate encoding="iso8601">20241112113610.0</recordChangeDate>
  </recordInfo>
</mods>
