TY  - BOOK
AU  - Sayak Maity
AU  - Under supervision of Dr. Rakesh Palisetty
TI  - FPGA Implementation of a fault-tolerant RISC-V processor
PY  - 2025///
CY  - Shiv Nadar University, Dadri
PB  - Department of Electrical Engineering, School of Engineering
KW  - EngineeringElectrical EngineeringElectronics and Communication Engineering
ER  -