TY  - BOOK
AU  - Aditya Chechi;Prithviraj Varma Konduru
AU  - Under supervision of Dr. Rakesh Palisetty
TI  - ASIC implementation of five stage pipelined RISC-V processor core
PY  - 2025///
CY  - Shiv Nadar University, Dadri
PB  - Department of Electrical Engineering, School of Engineering
KW  - EngineeringElectrical EngineeringElectronics and Communication Engineering
ER  -