<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[SNU Library Search for 'index-term-genre:&quot; Verilog (Computer hardware description language)&quot;']]> </title> <link> https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=index-term-genre%3A%22%20Verilog%20%28Computer%20hardware%20description%20language%29%22&#38;sort_by=&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=index-term-genre%3A%22%20Verilog%20%28Computer%20hardware%20description%20language%29%22&#38;sort_by=&#38;format=rss"/> <description> <![CDATA[ Search results for 'index-term-genre:&quot; Verilog (Computer hardware description language)&quot;' at SNU Library]]> </description> <opensearch:totalResults>12</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=index-term-genre%3A%22%20Verilog%20%28Computer%20hardware%20description%20language%29%22&#38;sort_by=&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dindex-term-genre%253A%2522%2520Verilog%2520%2528Computer%2520hardware%2520description%2520language%2529%2522" startPage="" /> <item> <title> SystemVerilog for verification : a guide to learning the testbench language features </title> <dc:identifier>ISBN:9780387270364</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11685</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0387270361.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Spear, Chris..<br /> New York, NY : Springer, 2006 .<br /> xxxiv, 301 p. ; 25 cm..<br /> 9780387270364 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11685">Place hold on <em>SystemVerilog for verification</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11685</guid> </item> <item> <title> Verilog HDL : a guide to digital design and synthesis </title> <dc:identifier>ISBN:9788129700926</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11736</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8129700921.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar, Samir.<br /> Delhi Pearson Education(Singapore) 2004 .<br /> xlii, 450 p. ; 25 cm..<br /> 9788129700926 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11736">Place hold on <em>Verilog HDL </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11736</guid> </item> <item> <title> Verilog designer&#39;s library </title> <dc:identifier>ISBN:9780130811547</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11904</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0130811548.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Zeidman, Bob.<br /> Upper Saddle River : Prentice Hall, 1999 .<br /> xv, 411 p. ; 25 cm..<br /> 9780130811547 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11904">Place hold on <em>Verilog designer&#39;s library</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11904</guid> </item> <item> <title> Verification methodology manual for SystemVerilog </title> <dc:identifier>ISBN:9780387255385</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=14879</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0387255389.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bergeron, Janick...[et al].<br /> New York : Springer, 2006 .<br /> xvii, 503 p. ; 24 cm..<br /> 9780387255385 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=14879">Place hold on <em>Verification methodology manual for SystemVerilog</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=14879</guid> </item> <item> <title> PRINCIPLES OF VERILOG PLI </title> <dc:identifier>ISBN:9780792384779</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=16098</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792384776.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Mittra, Swapnajit.<br /> Boston Kluwer Academic Publishers 1999 .<br /> xxviii, 372 p. 24 cm..<br /> 9780792384779 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=16098">Place hold on <em>PRINCIPLES OF VERILOG PLI</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=16098</guid> </item> <item> <title> Real world FPGA design with Verilog </title> <dc:identifier>ISBN:9780130998514</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21814</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0130998516.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Coffman, Ken, 1953-.<br /> Upper Saddle River, NJ Prentice Hall PTR 2000 .<br /> xv, 291 p. 25 cm..<br /> 9780130998514 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=21814">Place hold on <em>Real world FPGA design with Verilog</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21814</guid> </item> <item> <title> HDL chip design : a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog </title> <dc:identifier>ISBN:9780965193438</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23192</link> <description> <![CDATA[ <p> By Smith, Douglas J. | Zamfirescu, Alex.<br /> Madison, AL Doone Publications 1996 .<br /> xvi, 448 p. 29 cm..<br /> 9780965193438 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23192">Place hold on <em>HDL chip design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23192</guid> </item> <item> <title> The Verilog hardware description language : Fourth edition </title> <dc:identifier>ISBN:9780792381662</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24211</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792381661.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Thomas, D. E. (Donald E.), 1951- | Moorby, Philip R., 1953-.<br /> Boston Kluwer Academic Publishers 1998 .<br /> xvi, 354 p. 24 cm..<br /> 9780792381662 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=24211">Place hold on <em>The Verilog hardware description language</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24211</guid> </item> <item> <title> The Verilog hardware description language </title> <dc:identifier>ISBN:0792391268</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33435</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792391268.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Thomas, Donald E. | Moorby, Philip.<br /> Boston, MA Kluwer Academic Publishers 1991 .<br /> xiv, 223 p. ; 25 cm..<br /> 0792391268 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=33435">Place hold on <em>The Verilog hardware description language</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33435</guid> </item> <item> <title> Advanced Digital Design with the Verilog HDL </title> <dc:identifier>ISBN:9788120327566</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41243</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/812032756X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ciletti, Michael D.<br /> New Delhi :PHI Learning 2014 .<br /> xxi,982p. 24cm. .<br /> 9788120327566 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=41243">Place hold on <em>Advanced Digital Design with the Verilog HDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41243</guid> </item> <item> <title> Verilog styles for synthesis of digital systems </title> <dc:identifier>ISBN:9780201618600</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41886</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0201618605.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Smith, David Richard | Franzon, Paul D..<br /> New Jersey :Prentic Hall 2000 .<br /> xiv, 314p. 24cm. .<br /> 9780201618600 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=41886">Place hold on <em>Verilog styles for synthesis of digital systems</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41886</guid> </item> <item> <title> Verilog by example : a concise introduction for FPGA design </title> <dc:identifier>ISBN:9780983497301</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=42140</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0983497303.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Readler, Blaine C..<br /> USA Full Arc Press, 2011 .<br /> 114p. 24cm. .<br /> 9780983497301 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=42140">Place hold on <em>Verilog by example </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=42140</guid> </item> </channel> </rss>
