<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[SNU Library Search for 'index-term-genre:&quot;Computer Hardware&quot;']]> </title> <link> https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=index-term-genre%3A%22Computer%20Hardware%22&#38;sort_by=&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=index-term-genre%3A%22Computer%20Hardware%22&#38;sort_by=&#38;format=rss"/> <description> <![CDATA[ Search results for 'index-term-genre:&quot;Computer Hardware&quot;' at SNU Library]]> </description> <opensearch:totalResults>32</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=index-term-genre%3A%22Computer%20Hardware%22&#38;sort_by=&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dindex-term-genre%253A%2522Computer%2520Hardware%2522" startPage="" /> <item> <title> Designing Embedded Hardware </title> <dc:identifier>ISBN:8173665664</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11275</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8173665664.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Catsoulis, John.<br /> Navi Mumbai Shroff Publication 2004 .<br /> xviii, 298p. 23cm . .<br /> 8173665664 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11275">Place hold on <em>Designing Embedded Hardware </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11275</guid> </item> <item> <title> SystemVerilog for verification : a guide to learning the testbench language features </title> <dc:identifier>ISBN:9780387270364</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11685</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0387270361.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Spear, Chris..<br /> New York, NY : Springer, 2006 .<br /> xxxiv, 301 p. ; 25 cm..<br /> 9780387270364 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11685">Place hold on <em>SystemVerilog for verification</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11685</guid> </item> <item> <title> Verilog HDL : a guide to digital design and synthesis </title> <dc:identifier>ISBN:9788129700926</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11736</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8129700921.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar, Samir.<br /> Delhi Pearson Education(Singapore) 2004 .<br /> xlii, 450 p. ; 25 cm..<br /> 9788129700926 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11736">Place hold on <em>Verilog HDL </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11736</guid> </item> <item> <title> VHDL for programmable logic </title> <dc:identifier>ISBN:9780201895735</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11772</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0201895730.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Skahill, Kevin.<br /> Reading, Mass. : Addison-Wesley, 1996 .<br /> xiv, 593 p. ; 24 cm. .<br /> 9780201895735 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11772">Place hold on <em>VHDL for programmable logic</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11772</guid> </item> <item> <title> Verilog designer&#39;s library </title> <dc:identifier>ISBN:9780130811547</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11904</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0130811548.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Zeidman, Bob.<br /> Upper Saddle River : Prentice Hall, 1999 .<br /> xv, 411 p. ; 25 cm..<br /> 9780130811547 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11904">Place hold on <em>Verilog designer&#39;s library</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11904</guid> </item> <item> <title> Chip-level modeling with VHDL </title> <dc:identifier>ISBN:0131331906</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12281</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0131331906.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Armstrong, James R..<br /> Englewood Cliffs, N.J. : Prentice Hall, 1989 .<br /> x, 148 p. ; 24 cm..<br /> 0131331906 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=12281">Place hold on <em>Chip-level modeling with VHDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12281</guid> </item> <item> <title> Writing testbenches :functional verification of HDL models </title> <dc:identifier>ISBN:9781402074011</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12482</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1402074018.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bergeron, Janick.<br /> Boston : Kluwer Academic Publishers, 2003 .<br /> xxx, 475 p. ; 25 cm..<br /> 9781402074011 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=12482">Place hold on <em>Writing testbenches </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12482</guid> </item> <item> <title> VHDL </title> <dc:identifier>ISBN:9780070445406</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=13158</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070445400.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Perry, Douglas L..<br /> New York : McGraw-Hill 1998 .<br /> xvi, 493 p. ; 25 cm.<br /> 9780070445406 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=13158">Place hold on <em>VHDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=13158</guid> </item> <item> <title> Handbook of data communications. </title> <dc:identifier>ISBN:9780850123630</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=13581</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0850123631.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bleazard, G. B..<br /> Manchester : NCC Publications, 1982 .<br /> xx, 477 p. ; 22 cm..<br /> 9780850123630 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=13581">Place hold on <em>Handbook of data communications.</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=13581</guid> </item> <item> <title> VHDL design representation and synthesis </title> <dc:identifier>ISBN:9780130216700</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=13801</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0130216704.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By James R Armstrong | / F Gail Gray.<br /> Upper Saddle River, NJ : Prentice Hall PTR 2000 .<br /> xv, 651 p. ; 25 cm. .<br /> 9780130216700 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=13801">Place hold on <em>VHDL design representation and synthesis</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=13801</guid> </item> <item> <title> Verification methodology manual for SystemVerilog </title> <dc:identifier>ISBN:9780387255385</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=14879</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0387255389.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bergeron, Janick...[et al].<br /> New York : Springer, 2006 .<br /> xvii, 503 p. ; 24 cm..<br /> 9780387255385 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=14879">Place hold on <em>Verification methodology manual for SystemVerilog</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=14879</guid> </item> <item> <title> PRINCIPLES OF VERILOG PLI </title> <dc:identifier>ISBN:9780792384779</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=16098</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792384776.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Mittra, Swapnajit.<br /> Boston Kluwer Academic Publishers 1999 .<br /> xxviii, 372 p. 24 cm..<br /> 9780792384779 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=16098">Place hold on <em>PRINCIPLES OF VERILOG PLI</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=16098</guid> </item> <item> <title> Real world FPGA design with Verilog </title> <dc:identifier>ISBN:9780130998514</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21814</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0130998516.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Coffman, Ken, 1953-.<br /> Upper Saddle River, NJ Prentice Hall PTR 2000 .<br /> xv, 291 p. 25 cm..<br /> 9780130998514 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=21814">Place hold on <em>Real world FPGA design with Verilog</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21814</guid> </item> <item> <title> A VHDL primer </title> <dc:identifier>ISBN:9780130965752</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21856</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0130965758.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bhasker, Jayaram.<br /> Upper Saddle River, NJ. Prentice Hall 1999 .<br /> xx, 373 p. 24 cm..<br /> 9780130965752 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=21856">Place hold on <em>A VHDL primer</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21856</guid> </item> <item> <title> The designer&#39;s guide to VHDL </title> <dc:identifier>ISBN:9788181471925</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23036</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/818147192X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ashenden, Peter J..<br /> an Francisco, CA : Morgan Kaufmann, 2002 .<br /> xxiv, 759 p. ; 24 cm..<br /> 9788181471925 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23036">Place hold on <em>The designer&#39;s guide to VHDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23036</guid> </item> <item> <title> Writing testbenches : functional verification of HDL models </title> <dc:identifier>ISBN:9780792377665</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23038</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792377664.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bergeron, Janick.<br /> Boston Kluwer Academic 2000 .<br /> xxii, 354 p. 24 cm..<br /> 9780792377665 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23038">Place hold on <em>Writing testbenches</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23038</guid> </item> <item> <title> HDL chip design : a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog </title> <dc:identifier>ISBN:9780965193438</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23192</link> <description> <![CDATA[ <p> By Smith, Douglas J. | Zamfirescu, Alex.<br /> Madison, AL Doone Publications 1996 .<br /> xvi, 448 p. 29 cm..<br /> 9780965193438 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23192">Place hold on <em>HDL chip design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23192</guid> </item> <item> <title> VHDL analysis and modeling of digital systems </title> <dc:identifier>ISBN:9780070464797</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23233</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070464790.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Navabi, Zainalabedin.<br /> New York ; McGraw-Hill, 1998 .<br /> xxii, 632 p. ; 24 cm..<br /> 9780070464797 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23233">Place hold on <em>VHDL </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23233</guid> </item> <item> <title> The Verilog hardware description language : Fourth edition </title> <dc:identifier>ISBN:9780792381662</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24211</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792381661.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Thomas, D. E. (Donald E.), 1951- | Moorby, Philip R., 1953-.<br /> Boston Kluwer Academic Publishers 1998 .<br /> xvi, 354 p. 24 cm..<br /> 9780792381662 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=24211">Place hold on <em>The Verilog hardware description language</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24211</guid> </item> <item> <title> Mike Meyers&#39; A+ guide to PC hardware </title> <dc:identifier>ISBN:9780072231199</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24687</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/007223119X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Meyers, Michael, 1961- | Jernigan, Scott.<br /> New York McGraw-Hill Technology Education 2004 .<br /> xix, 586 p. ; 28 cm. + 1 CD-ROM (4 3/4 in.).<br /> 9780072231199 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=24687">Place hold on <em>Mike Meyers&#39; A+ guide to PC hardware</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24687</guid> </item> <item> <title> Digital systems design using VHDL </title> <dc:identifier>ISBN:9789812400529</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33428</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/9812400524.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Roth Jr., Charles H..<br /> Boston, MA PWS Pub. Co. 1998 .<br /> x, 470 p. ; 25 cm..<br /> 9789812400529 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=33428">Place hold on <em>Digital systems design using VHDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33428</guid> </item> <item> <title> The Verilog hardware description language </title> <dc:identifier>ISBN:0792391268</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33435</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792391268.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Thomas, Donald E. | Moorby, Philip.<br /> Boston, MA Kluwer Academic Publishers 1991 .<br /> xiv, 223 p. ; 25 cm..<br /> 0792391268 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=33435">Place hold on <em>The Verilog hardware description language</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33435</guid> </item> <item> <title> The art of verification with Vera </title> <dc:identifier>ISBN:097119940X</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=38424</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/097119940X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Haque, Faisal I...[et al].<br /> Fremont, Calif. : Verification Central, 2001 .<br /> xxiv, 452 p. ; 23 cm..<br /> 097119940X </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=38424">Place hold on <em>The art of verification with Vera</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=38424</guid> </item> <item> <title> SCO Hardware Comparability Handbook </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39482</link> <description> <![CDATA[ <p> By /SCO.<br /> .-California :The Santa Cruz Operation, Inc. 1996 .<br /> 212p.;15cm. </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=39482">Place hold on <em>SCO Hardware Comparability Handbook </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39482</guid> </item> <item> <title> Shells: user guide ; HP 9000 Computers </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39536</link> <description> <![CDATA[ <p> By Hewlett Packard .<br /> .-USA : Hewlett Packard Company 1980 .<br /> iii,ind-14p.;15cm. </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=39536">Place hold on <em>Shells: user guide</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39536</guid> </item> <item> <title> Sun keyboard and mouse </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39648</link> <description> <![CDATA[ <p> By Sun Microsystems.<br /> .<br /> vi,zh_TW-8p.;12cm. </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=39648">Place hold on <em>Sun keyboard and mouse</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39648</guid> </item> <item> <title> LCA Applications handbook </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39839</link> <description> <![CDATA[ <p> By monolithic .<br /> .-USA :monolithic memories 1998 .<br /> 6-8p.;15cm. </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=39839">Place hold on <em>LCA Applications handbook</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39839</guid> </item> <item> <title> 1996 DRAM Data Book </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39884</link> <description> <![CDATA[ <p> By Micron Technology .Inc..<br /> .-USA :Micron Technology .Inc. 1995 .<br /> xxii,11-8p.;15cm. </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=39884">Place hold on <em>1996 DRAM Data Book</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39884</guid> </item> <item> <title> System Assembly and maintenance : Part V </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=40594</link> <description> <![CDATA[ <p> By Hewlett Packard .<br /> .-USA : Hewlett Packard, Inc. 1998 .<br /> 1546p.;10cm. </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=40594">Place hold on <em>System Assembly and maintenance </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=40594</guid> </item> <item> <title> Advanced Digital Design with the Verilog HDL </title> <dc:identifier>ISBN:9788120327566</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41243</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/812032756X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ciletti, Michael D.<br /> New Delhi :PHI Learning 2014 .<br /> xxi,982p. 24cm. .<br /> 9788120327566 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=41243">Place hold on <em>Advanced Digital Design with the Verilog HDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41243</guid> </item> <item> <title> Verilog styles for synthesis of digital systems </title> <dc:identifier>ISBN:9780201618600</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41886</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0201618605.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Smith, David Richard | Franzon, Paul D..<br /> New Jersey :Prentic Hall 2000 .<br /> xiv, 314p. 24cm. .<br /> 9780201618600 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=41886">Place hold on <em>Verilog styles for synthesis of digital systems</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41886</guid> </item> <item> <title> Verilog by example : a concise introduction for FPGA design </title> <dc:identifier>ISBN:9780983497301</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=42140</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0983497303.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Readler, Blaine C..<br /> USA Full Arc Press, 2011 .<br /> 114p. 24cm. .<br /> 9780983497301 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=42140">Place hold on <em>Verilog by example </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=42140</guid> </item> </channel> </rss>
