<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[SNU Library Search for 'su:&quot;CAD for VLSI Design II&quot;']]> </title> <link> https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22CAD%20for%20VLSI%20Design%20II%22&#38;sort_by=&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22CAD%20for%20VLSI%20Design%20II%22&#38;sort_by=&#38;format=rss"/> <description> <![CDATA[ Search results for 'su:&quot;CAD for VLSI Design II&quot;' at SNU Library]]> </description> <opensearch:totalResults>23</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22CAD%20for%20VLSI%20Design%20II%22&#38;sort_by=&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dsu%253A%2522CAD%2520for%2520VLSI%2520Design%2520II%2522" startPage="" /> <item> <title> CAD for VLSI Design II : Transistor Theory </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10983</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 1 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=10983">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10983</guid> </item> <item> <title> CAD for VLSI Design II : Introduction to MOSFET </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10984</link> <description> <![CDATA[ <p> By Kamakoti, V.and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 2 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=10984">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10984</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Fundamentals </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10985</link> <description> <![CDATA[ <p> By Kamakoti, V.and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 3 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=10985">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10985</guid> </item> <item> <title> CAD for VLSI Design II : Transistor Theory (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11037</link> <description> <![CDATA[ <p> By Kamakoti, V.and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 4 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11037">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11037</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Theory - Delay Issues </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11038</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 5 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11038">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11038</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Theory - Delay Issues (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11045</link> <description> <![CDATA[ <p> By V. Kamakoti and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 6 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11045">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11045</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Theory - Delay Models </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11047</link> <description> <![CDATA[ <p> By Kamakoti V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 7 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11047">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11047</guid> </item> <item> <title> CAD for VLSI Design II : Delay Elements in CMOS Circuits </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11048</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 8 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11048">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11048</guid> </item> <item> <title> CAD for VLSI Design II : Delay Elements in CMOS Circuits (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11049</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 9 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11049">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11049</guid> </item> <item> <title> CAD for VLSI Design II : Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11050</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 10 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11050">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11050</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11051</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 11 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11051">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11051</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis - Synthesizable and Non Synthesizable constructs </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11054</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 12 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11054">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11054</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis - Logic Optimization, Resource Sharing </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11055</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 13 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11055">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11055</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis - Logic Optimization, Resource Sharing (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11057</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 14 , pdf lecture.<br /> </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11057">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11057</guid> </item> <item> <title> CAD for VLSI Design II : Flip Flop and Latch optimaztion </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11059</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 15 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11059">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11059</guid> </item> <item> <title> CAD for VLSI Design II : Introduction to Logical Effort </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11061</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 16 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11061">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11061</guid> </item> <item> <title> CAD for VLSI Design II : Multistage Logic Networks </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11062</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 17 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11062">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11062</guid> </item> <item> <title> CAD for VLSI Design II : Logical effort - Optimizing performance </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11063</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 19 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11063">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11063</guid> </item> <item> <title> CAD for VLSI Design II : Logical Effort and Gain based Synthesis (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11064</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 20 , pdf lecture.<br /> </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11064">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11064</guid> </item> <item> <title> CAD for VLSI Design II : MAGMA ASIC Design Flow Stage 1 </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11065</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> MAGMA Tutorial </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11065">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11065</guid> </item> <item> <title> CAD for VLSI Design II : MAGMA ASIC Design Flow Stage 2 </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11066</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> MAGMA Tutorial </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11066">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11066</guid> </item> <item> <title> CAD for VLSI Design II : MAGMA ASIC Design Flow Stage 3 </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11067</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> MAGMA Tutorial </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11067">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11067</guid> </item> <item> <title> CAD for VLSI Design II : Project - Superscalar Processor Implementation </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11068</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Project </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11068">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11068</guid> </item> </channel> </rss>
