<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[SNU Library Search for 'su:&quot;HDL&quot;']]> </title> <link> https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22HDL%22&#38;sort_by=&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22HDL%22&#38;sort_by=&#38;format=rss"/> <description> <![CDATA[ Search results for 'su:&quot;HDL&quot;' at SNU Library]]> </description> <opensearch:totalResults>6</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22HDL%22&#38;sort_by=&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dsu%253A%2522HDL%2522" startPage="" /> <item> <title> Application-Specific Integrated Circuits </title> <dc:identifier>ISBN:9788177584080</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=133</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177584081.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Smith, Micheal John Sebestian.<br /> Delhi Pearson 2009 .<br /> 1039p. 9788177584080 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=133">Place hold on <em>Application-Specific Integrated Circuits</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=133</guid> </item> <item> <title> Writing testbenches :functional verification of HDL models </title> <dc:identifier>ISBN:9781402074011</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12482</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1402074018.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bergeron, Janick.<br /> Boston : Kluwer Academic Publishers, 2003 .<br /> xxx, 475 p. ; 25 cm..<br /> 9781402074011 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=12482">Place hold on <em>Writing testbenches </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12482</guid> </item> <item> <title> Writing testbenches : functional verification of HDL models </title> <dc:identifier>ISBN:9780792377665</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23038</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792377664.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Bergeron, Janick.<br /> Boston Kluwer Academic 2000 .<br /> xxii, 354 p. 24 cm..<br /> 9780792377665 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23038">Place hold on <em>Writing testbenches</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23038</guid> </item> <item> <title> HDL chip design : a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog </title> <dc:identifier>ISBN:9780965193438</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23192</link> <description> <![CDATA[ <p> By Smith, Douglas J. | Zamfirescu, Alex.<br /> Madison, AL Doone Publications 1996 .<br /> xvi, 448 p. 29 cm..<br /> 9780965193438 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=23192">Place hold on <em>HDL chip design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=23192</guid> </item> <item> <title> Advanced Digital Design with the Verilog HDL </title> <dc:identifier>ISBN:9788120327566</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41243</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/812032756X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ciletti, Michael D.<br /> New Delhi :PHI Learning 2014 .<br /> xxi,982p. 24cm. .<br /> 9788120327566 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=41243">Place hold on <em>Advanced Digital Design with the Verilog HDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41243</guid> </item> <item> <title> Verilog HDL : a guide to digital design and synthesis, IEEE 1364-2001 complaint. </title> <dc:identifier>ISBN:9788177589184</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=62555</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177589180.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar, Samir | ; Goel, Prabhu..<br /> , Noida : Pearson 2022 .<br /> 490p. : 24cm..<br /> 9788177589184 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=62555">Place hold on <em>Verilog HDL</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=62555</guid> </item> </channel> </rss>
