<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[SNU Library Search for 'su:&quot;VLSI Design&quot;']]> </title> <link> https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22VLSI%20Design%22&#38;sort_by=&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22VLSI%20Design%22&#38;sort_by=&#38;format=rss"/> <description> <![CDATA[ Search results for 'su:&quot;VLSI Design&quot;' at SNU Library]]> </description> <opensearch:totalResults>40</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="https://library.snu.edu.in/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22VLSI%20Design%22&#38;sort_by=&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dsu%253A%2522VLSI%2520Design%2522" startPage="" /> <item> <title> CMOS VLSI Design A Circuits and Systems Perspective </title> <dc:identifier>ISBN:9788177585681</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=181</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177585681.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Weste, Neil H.E. | Harris, David | Banerjee, Ayan.<br /> New Delhi Pearson 2009 .<br /> xvii; 659p. 9788177585681 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=181">Place hold on <em>CMOS VLSI Design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=181</guid> </item> <item> <title> Low Voltage, Low Power, VLSI Subsystems </title> <dc:identifier>ISBN:9780070677500</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=186</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070677506.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Yeo, Kiat-Seng | ; Roy, Kaushik.<br /> New Delhi : TMH, 2009 .<br /> xxi, 293p. 9780070677500 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=186">Place hold on <em>Low Voltage, Low Power, VLSI Subsystems</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=186</guid> </item> <item> <title> CMOS VLSI Design A Circuits and Systems Perspective </title> <dc:identifier>ISBN:9788177585681</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=204</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177585681.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Waste, Neil H.E. | Harris, David | Banerjee, Ayan.<br /> New Delhi Pearson 2009 .<br /> xvii; 659p. 9788177585681 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=204">Place hold on <em>CMOS VLSI Design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=204</guid> </item> <item> <title> VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS </title> <dc:identifier>ISBN:9780070702486</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=248</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070702489.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Geinger , Randall L. | Allen, Phillip E. | Strader,Noel R..<br /> Delhi TMH 2010 .<br /> xv;965 p. 9780070702486 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=248">Place hold on <em>VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=248</guid> </item> <item> <title> Basic VLSI Design </title> <dc:identifier>ISBN:9788120309869</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=3901</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8120309863.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Dauglas A.Pucknell | Eshraghian, Kamran .<br /> New Delhi :PHI Learning Privet Limited 2013 .<br /> xix;459p. 9788120309869 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=3901">Place hold on <em>Basic VLSI Design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=3901</guid> </item> <item> <title> CMOS VLSI Design : A Circuits and Systems Perspective </title> <dc:identifier>ISBN:9788177585681</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=5724</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177585681.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Waste, Neil H. E. | Harris, David | Banergee, Ayan.<br /> New Delhi Pearson 2012 .<br /> xxi; 659p. 9788177585681 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=5724">Place hold on <em>CMOS VLSI Design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=5724</guid> </item> <item> <title> CAD for VLSI Design II : Transistor Theory </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10983</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 1 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=10983">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10983</guid> </item> <item> <title> CAD for VLSI Design II : Introduction to MOSFET </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10984</link> <description> <![CDATA[ <p> By Kamakoti, V.and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 2 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=10984">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10984</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Fundamentals </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10985</link> <description> <![CDATA[ <p> By Kamakoti, V.and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 3 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=10985">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=10985</guid> </item> <item> <title> CAD for VLSI Design II : Transistor Theory (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11037</link> <description> <![CDATA[ <p> By Kamakoti, V.and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 4 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11037">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11037</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Theory - Delay Issues </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11038</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 5 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11038">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11038</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Theory - Delay Issues (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11045</link> <description> <![CDATA[ <p> By V. Kamakoti and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 6 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11045">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11045</guid> </item> <item> <title> CAD for VLSI Design II : CMOS Transistor Theory - Delay Models </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11047</link> <description> <![CDATA[ <p> By Kamakoti V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 7 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11047">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11047</guid> </item> <item> <title> CAD for VLSI Design II : Delay Elements in CMOS Circuits </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11048</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 8 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11048">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11048</guid> </item> <item> <title> CAD for VLSI Design II : Delay Elements in CMOS Circuits (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11049</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 9 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11049">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11049</guid> </item> <item> <title> CAD for VLSI Design II : Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11050</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 10 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11050">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11050</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11051</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 11 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11051">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11051</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis - Synthesizable and Non Synthesizable constructs </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11054</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 12 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11054">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11054</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis - Logic Optimization, Resource Sharing </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11055</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 13 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11055">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11055</guid> </item> <item> <title> CAD for VLSI Design II : Synthesis - Logic Optimization, Resource Sharing (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11057</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 14 , pdf lecture.<br /> </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11057">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11057</guid> </item> <item> <title> CAD for VLSI Design II : Flip Flop and Latch optimaztion </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11059</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 15 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11059">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11059</guid> </item> <item> <title> CAD for VLSI Design II : Introduction to Logical Effort </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11061</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 16 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11061">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11061</guid> </item> <item> <title> CAD for VLSI Design II : Multistage Logic Networks </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11062</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 17 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11062">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11062</guid> </item> <item> <title> CAD for VLSI Design II : Logical effort - Optimizing performance </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11063</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 19 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11063">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11063</guid> </item> <item> <title> CAD for VLSI Design II : Logical Effort and Gain based Synthesis (Contd) </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11064</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Chapter 20 , pdf lecture.<br /> </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11064">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11064</guid> </item> <item> <title> CAD for VLSI Design II : MAGMA ASIC Design Flow Stage 1 </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11065</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> MAGMA Tutorial </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11065">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11065</guid> </item> <item> <title> CAD for VLSI Design II : MAGMA ASIC Design Flow Stage 2 </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11066</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> MAGMA Tutorial </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11066">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11066</guid> </item> <item> <title> CAD for VLSI Design II : MAGMA ASIC Design Flow Stage 3 </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11067</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> MAGMA Tutorial </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11067">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11067</guid> </item> <item> <title> CAD for VLSI Design II : Project - Superscalar Processor Implementation </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11068</link> <description> <![CDATA[ <p> By Kamakoti, V. and Balachandran, Shankar.<br /> IIT Madras ; Indian Institute of Technology Madras .<br /> Project </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=11068">Place hold on <em>CAD for VLSI Design II</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=11068</guid> </item> <item> <title> Modern VLSI design : a systems approach </title> <dc:identifier>ISBN:9788178086538</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12559</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8178086530.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Wolf,Wayne.<br /> Newdelhi Pearson publications 2003 .<br /> xx, 618 p. ; 24 cm..<br /> 9788178086538 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=12559">Place hold on <em>Modern VLSI design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=12559</guid> </item> <item> <title> Principles of CMOS VLSI design : a systems perspective </title> <dc:identifier>ISBN:9780201533767</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21887</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0201533766.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Weste, Neil H. E. | Eshraghian, Kamran | Eshraghian, K..<br /> Reading, Mass. Addison-Wesley 1985 .<br /> xxii, 531 p. 24 cm..<br /> 9780201533767 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=21887">Place hold on <em>Principles of CMOS VLSI design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=21887</guid> </item> <item> <title> A priori wire length estimates for digital design </title> <dc:identifier>ISBN:9780792373605</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24180</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/079237360X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Stroobandt, Dirk.<br /> Boston Kluwer Academic Publishers 2001 .<br /> xxii, 298 p. 25 cm..<br /> 9780792373605 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=24180">Place hold on <em>A priori wire length estimates for digital design</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24180</guid> </item> <item> <title> Interconnects in VLSI design </title> <dc:identifier>ISBN:9780792379973</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24391</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0792379977.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Grabinski, Hartmut;.<br /> Boston : Kluwer Academic Publishers 2000 .<br /> vi, 236 p. ; 25 cm..<br /> 9780792379973 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=24391">Place hold on <em>Interconnects in VLSI design </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=24391</guid> </item> <item> <title> VLSI Technology: Introduction on VLSI Design </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=26106</link> <description> <![CDATA[ <p> By Dasgupta, Nandita.<br /> Madras Indian Insitiute of Technology </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=26106">Place hold on <em>VLSI Technology:</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=26106</guid> </item> <item> <title> VLSI Technology: Introduction on VLSI Design </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=30199</link> <description> <![CDATA[ <p> By Dasgupta, Nandita.<br /> Madras Indian Insitiute of Technology </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=30199">Place hold on <em>VLSI Technology:</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=30199</guid> </item> <item> <title> Design Verification and Test of Digital VLSI Circuits: Introduction to Digital VLSI Design Flow </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33967</link> <description> <![CDATA[ <p> By &quot;Biswas, Santosh&quot; | &quot;Deka, Jatindra Kumar&quot;.<br /> Guwahati Indian Insitiute of Technology </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=33967">Place hold on <em>Design Verification and Test of Digital VLSI Circuits:</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=33967</guid> </item> <item> <title> VLSI Design 2000 :Thirteenth international conference on VLSI design </title> <dc:identifier>ISBN:9780769504872</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39053</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0769504876.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Computer Society..<br /> India. ,The institue of electrical and electronics engineers,Inc.. 2000 .<br /> xxxiv,588p. ;28cm..<br /> 9780769504872 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=39053">Place hold on <em>VLSI Design 2000 </em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=39053</guid> </item> <item> <title> 7th Asia and South Pacific Design Automation Conference : 7-11 January 2002. Bangalore, India. </title> <dc:identifier>ISBN:</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41907</link> <description> <![CDATA[ <p> By IEEE Computer Society.<br /> Washington : IEEE Computer Society 2002 .<br /> xxx; 810p. , 30 cm..<br /> </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=41907">Place hold on <em>7th Asia and South Pacific Design Automation Conference</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=41907</guid> </item> <item> <title> Introduction to VLSI design and technology </title> <dc:identifier>ISBN:978122430646</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=44568</link> <description> <![CDATA[ <p> By Roy, J. N. | Bose, D. N. .<br /> New Delhi :New Age International Pub. 2011 .<br /> xiv, 488p. 24cm. .<br /> 978122430646 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=44568">Place hold on <em>Introduction to VLSI design and technology</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=44568</guid> </item> <item> <title> Introduction to VLSI Design Flow </title> <dc:identifier>ISBN:9781009200813</dc:identifier> <link>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=62506</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/100920081X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Saurabh, Sneh..<br /> , New York : Cambridge University Press 2024 .<br /> xxiv, 689p. : 28cm..<br /> 9781009200813 </p> ]]> <![CDATA[ <p> <a href="https://library.snu.edu.in/cgi-bin/koha/opac-reserve.pl?biblionumber=62506">Place hold on <em>Introduction to VLSI Design Flow</em></a> </p> ]]> </description> <guid>https://library.snu.edu.in/cgi-bin/koha/opac-detail.pl?biblionumber=62506</guid> </item> </channel> </rss>
