000			01028nam a22002417a 4500
003			SNU
005			20140609174359.0
040			_aNPTEL _cIIT Madras
082			_a004
100			_aKamakoti, V. and Balachandran, Shankar
245			_aCAD for VLSI Design II _b: Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis _c/ V. Kamakoti and Shankar Balachandran
260			_aIIT Madras _b; Indian Institute of Technology Madras
300			_aChapter 10 _b; 20 p. _f, pdf lecture
440			_aNPTEL Lecture Series _n , Chapter 10 _p: Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis
650			_aEstimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis
650			_aCAD for VLSI Design II
650			_aComputer Science & Engineering
650			_aNPTEL
650			_aV. Kamakoti and Shankar Balachandran
650			_aIIT Madras
856			_3pdf _uhttp://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/pdf/nptel-cad2-10.pdf
942			_2ddc _cNPTEL
999			_c11050 _d11050