| 000 | 00895nam a22002417a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20140609174707.0 | ||
| 040 |
_aNPTEL _cIIT Madras |
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| 082 | _a004 | ||
| 100 | _aKamakoti, V. and Balachandran, Shankar | ||
| 245 |
_aCAD for VLSI Design II _b: Flip Flop and Latch optimaztion _c/ V. Kamakoti and Shankar Balachandran |
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| 260 |
_aIIT Madras _b; Indian Institute of Technology Madras |
||
| 300 |
_aChapter 15 _b; 19 p. _f, pdf lecture |
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| 440 |
_aNPTEL Lecture Series _n, Chapter 15 _p: Flip Flop and Latch optimaztion |
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| 650 | _aFlip Flop and Latch optimaztion | ||
| 650 | _aCAD for VLSI Design II | ||
| 650 | _aComputer Science & Engineering | ||
| 650 | _aNPTEL | ||
| 650 | _aV. Kamakoti and Shankar Balachandran | ||
| 650 | _aIIT Madras | ||
| 856 |
_3pdf _uhttp://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/pdf/nptel-cad2-15.pdf |
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| 942 |
_2ddc _cNPTEL |
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| 999 |
_c11059 _d11059 |
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