| 000 | 00919nam a22002417a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20140609175148.0 | ||
| 040 |
_aNPTEL _cIIT Madras |
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| 082 | _a004 | ||
| 100 | _aKamakoti, V. and Balachandran, Shankar | ||
| 245 |
_aCAD for VLSI Design II _b: Logical effort - Optimizing performance _c/ V. Kamakoti and Shankar Balachandran |
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| 260 |
_aIIT Madras _b; Indian Institute of Technology Madras |
||
| 300 |
_aChapter 19 _b; 23 p. _f, pdf lecture |
||
| 440 |
_aNPTEL Lecture Series _n, Chapter 19 _p: Logical Effort and Gain based Synthesis |
||
| 650 | _aLogical Effort and Gain based Synthesis | ||
| 650 | _aCAD for VLSI Design II | ||
| 650 | _aComputer Science & Engineering | ||
| 650 | _aNPTEL | ||
| 650 | _aV. Kamakoti and Shankar Balachandran | ||
| 650 | _aIIT Madras | ||
| 856 |
_3pdf _uhttp://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/pdf/nptel-cad2-19.pdf |
||
| 942 |
_2ddc _cNPTEL |
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| 999 |
_c11063 _d11063 |
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