| 000 | 00816nam a22002537a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20140625115714.0 | ||
| 008 | 140625b xxu||||| |||| 00| 0 eng d | ||
| 020 | _a9781402074011 | ||
| 028 | _aHCL | ||
| 082 | _a621.3815 BER | ||
| 100 | _aBergeron, Janick | ||
| 245 |
_aWriting testbenches _b:functional verification of HDL models _c/ Janick Bergeron |
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| 250 | _a2nd ed. | ||
| 260 |
_a Boston _b: Kluwer Academic Publishers, _c©2003. |
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| 300 |
_axxx, 475 p. _b: ill. _c; 25 cm. |
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| 655 | _aComputer hardware description languages. | ||
| 655 | _a Integrated circuits -- Verification. | ||
| 655 | _aAnálise de desempenho. | ||
| 655 | _acomputer science | ||
| 655 | _aWriting testbenches functional verification of HDL models | ||
| 655 | _aJanick Bergeron | ||
| 942 |
_2ddc _cHCL |
||
| 999 |
_c12482 _d12482 |
||