| 000 | 00636nam a22002177a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20140625172730.0 | ||
| 008 | 140625b xxu||||| |||| 00| 0 eng d | ||
| 020 | _a9780387292212 | ||
| 028 | _aHCL | ||
| 082 | _a621.392 BER | ||
| 100 | _aBergeron, Janick | ||
| 245 |
_aWriting testbenches using System Verilog _c/ Janick Bergeron |
||
| 260 |
_aNew York _b: Springer Science+Business Media, _c ©2006. |
||
| 300 |
_axxvi, 412 p. _b: ill. _c; 25 cm. |
||
| 655 | _aVerilog | ||
| 655 | _aIntegrated circuits -- Verification. | ||
| 655 | _aBergeron, Janick | ||
| 655 | _aElectrical Engineering | ||
| 942 |
_2ddc _cHCL |
||
| 999 |
_c12595 _d12595 |
||