| 000 | 00711nam a22002177a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20140710170329.0 | ||
| 008 | 140710b xxu||||| |||| 00| 0 eng d | ||
| 020 | _a9780387255385 | ||
| 028 | _aHCL | ||
| 082 | _a621.392 BER | ||
| 100 | _aBergeron, Janick...[et al] | ||
| 245 |
_aVerification methodology manual for SystemVerilog _c/ Janick Bergeron...[et al] |
||
| 260 |
_aNew York _b: Springer, _c©2006. |
||
| 300 |
_axvii, 503 p. _b: ill. _c ; 24 cm. |
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| 655 | _a Verilog (Computer hardware description language) | ||
| 655 | _a Integrated circuits -- Verification. | ||
| 655 | _aVerification methodology manual for SystemVerilog | ||
| 655 | _aJanick Bergeron | ||
| 942 |
_2ddc _cHCL |
||
| 999 |
_c14879 _d14879 |
||