000 00996nmm a2200241 a 4500
003 SNU
005 20140829184441.0
008 140822s9999 xx 000 0 und d
040 _aNPTEL
_cIIT Madras
100 _aSrinivasan, S.
245 _aVLSI Circuits:
_bModelling of Verilog Sequential Circuits - Core Statements
_c/ S. Srinivasan
260 _aMadras
_bIndian Insitiute of Technology
300 _fVideo Lecture
440 _aNPTEL Lecture Series
_nElectronics And Communication Engineering
_pModelling of Verilog Sequential Circuits - Core Statements
650 _aElectronics And Communication Engineering
650 _aIIT Madras
650 _aModelling of Verilog Sequential Circuits - Core Statements
650 _aNPTEL
650 _aProf. S. Srinivasan
650 _aVLSI Circuits
856 _3Video
_uhttp://video.snu.edu.in/index.php?id=4342&cat=Electronics And Communication Engineering&course=VLSI Circuits&url=Phase1_Video/117106092/lec11.mp4
942 _2ddc
_cNP SNU
999 _c30154
_d30154