| 000 | 01119nmm a2200253 a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20140915195140.0 | ||
| 008 | 140911s9999 xx 000 0 und d | ||
| 040 |
_aNPTEL _cIIT Guwahati |
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| 100 | _a"Biswas, Santosh" | ||
| 100 | _a"Deka, Jatindra Kumar" | ||
| 245 |
_aDesign Verification and Test of Digital VLSI Circuits: _bHigh Level Design Representation _c/ Jatindra Kumar Deka and Santosh Biswas |
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| 260 |
_aGuwahati _bIndian Insitiute of Technology |
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| 300 | _fVideo Lecture | ||
| 440 |
_aNPTEL Lecture Series _nComputer Science and Engineering _pHigh Level Design Representation |
||
| 650 | _a"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas" | ||
| 650 | _aComputer Science and Engineering | ||
| 650 | _aDesign Verification and Test of Digital VLSI Circuits | ||
| 650 | _aHigh Level Design Representation | ||
| 650 | _aIIT Guwahati | ||
| 650 | _aNPTEL | ||
| 856 |
_3Video _uhttp://video.snu.edu.in/index.php?id=7264&cat=Computer Science and Engineering&course=Design Verification and Test of Digital VLSI Circuits&url=Phase2_Video/106103116/mod01lec02.mp4 |
||
| 942 |
_2ddc _cNP SNU |
||
| 999 |
_c33968 _d33968 |
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