| 000 | 00657nam a22001697a 4500 | ||
|---|---|---|---|
| 003 | SNU | ||
| 005 | 20160108112223.0 | ||
| 008 | 150819b xxu||||| |||| 00| 0 eng d | ||
| 100 | _aMalik, Aditi | ||
| 245 |
_aProject on logical placer:An evolutionary approach for optimized standard cell placement in VLSI physical design automation. _c\Aditi Malik |
||
| 260 |
_a.-Shiv Nadar University,Dadri _b:Department of Electrical Engineering _c,May,2015 |
||
| 300 |
_a49 p. _b, Hard Bound |
||
| 440 |
_a.-(M.Tech Electrical Engineering) _n,Under Supervision of Dr. Naveen Babu |
||
| 655 | _aProject Report | ||
| 655 | _a Electrical Engineering | ||
| 942 |
_2ddc _cPR |
||
| 999 |
_c45010 _d45010 |
||