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| 003 | SNU | ||
| 005 | 20170117121840.0 | ||
| 008 | 161227b xxu||||| |||| 00| 0 eng d | ||
| 100 |
_aSrinivasan Anand _aV,Sundar _aVerma,Jagdeep |
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| 245 |
_aDesign Voltage Controlled Oscillators For Phase Lock loops (PLLs) _c/ Anand Srinivasan [ at al ] |
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_a.-Shiv Nadar University,Dadri _b:Department of Electrical Engineering _c:May 2016 |
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_a50p. _b, Hard Bound |
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_a.-(B.Tech Electrical Engineering) _n:,Under Supervision of Mr Sushrant Monga |
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| 655 | _aElectrical Engineering | ||
| 655 | _aProject Report | ||
| 856 | _uhttp://dspace.snu.edu.in:8080/jspui/handle/123456789/179 | ||
| 942 |
_2ddc _cPR |
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| 999 |
_c47381 _d47381 |
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