000			00530nam a2200157Ia 4500
999			_c51193 _d51193
005			20190625120906.0
008			190531s9999 xx 000 0 und d
100			_aRaasi Chenna
245		0	_aFPGA Simulation Environment for Pen Verification Module
260			_aShiv Nadar University _bElectronics and Communication Engineering _cMay-19
300			_a55 p. _b: Hard Bound. _c:29cm.
655			_aProject Report.
700			_aMadhur Upadhayay
856			_uhttp://dspace.snu.edu.in:8080/jspui/handle/123456789/582
942			_cPR