000			00568nam a22001697a 4500
005			20230613121958.0
008			230613b |||||||| |||| 00| 0 eng d
100			_aKunda, Chaitanya.
245			_aRTL Design and FPGA Implementation
260			_aShiv Nadar University, Dadri" _b"Department of Electrical Engineering, School of Engineering" _c2023.
300			_a27p. _c: 26cm.
650			_a Engineering
650			_aElectrical Engineering
650			_a Electronics and Communication Engineering
700			_aUnder Supervision of Dr. Rohit Singh.
942			_cPR
999			_c60336 _d60336