| 000 | 00661nam a22001817a 4500 | ||
|---|---|---|---|
| 005 | 20240903135838.0 | ||
| 008 | 240903b |||||||| |||| 00| 0 eng d | ||
| 100 | _aAditi Sharma | ||
| 245 | _aProcessor Design: From Specification to Gate- Level Netlist Realization | ||
| 260 |
_a " Shiv Nadar Institution of Eminence" _b"Department of Electrical and Electronic Engineering, School of Engineering" _cApril 2024. |
||
| 300 |
_a66p. _c: 26cm. |
||
| 650 | _a Engineering | ||
| 650 | _aElectrical Engineering | ||
| 650 | _aElectrical and Electronics Engineering | ||
| 650 | _aB.Tech. | ||
| 700 | _aUnder Supervision of Dr. Venkatnarayan Hariharan | ||
| 942 | _cPR | ||
| 999 |
_c62275 _d62275 |
||