000 00589nam a22001697a 4500
005 20240905105238.0
008 240905b |||||||| |||| 00| 0 eng d
100 _aKolli Sreeram Sai.
245 _aOptimizing Core Utilization Using Parallelization
260 _a" Shiv Nadar Institution of Eminence "
_b"Department of Electrical and Electronic Engineering, School of Engineering"
_c, Spring 2024.
300 _a18p.
_c: 26cm.
650 _aEngineering
650 _aElectrical Engineering
650 _aB.Tech.
700 _aUnder the Supervison of Dr. Rakesh Palisetty.
942 _cPR
999 _c62297
_d62297