| 000 | 00550nam a22001697a 4500 | ||
|---|---|---|---|
| 005 | 20240906111241.0 | ||
| 008 | 240906b |||||||| |||| 00| 0 eng d | ||
| 100 | _aRacharla Chayank. | ||
| 245 | _aIP Design for Image Processing Using VHDL. | ||
| 260 |
_a" Shiv Nadar University, Dadri" _b"Department of Electrical Engineering, School of Engineering" _c, April 2024. |
||
| 300 |
_a81p. _c: 26cm. |
||
| 650 | _aEngineering | ||
| 650 | _aElectrical Engineering | ||
| 650 | _aB.Tech. | ||
| 700 | _aUnder Supervision of Dr. Naveen Babu. | ||
| 942 | _cPR | ||
| 999 |
_c62333 _d62333 |
||