| 000 | 00552nam a2200133Ia 4500 | ||
|---|---|---|---|
| 008 | 250624s9999||||xx |||||||||||||| ||und|| | ||
| 100 | _aAditya Chechi;Prithviraj Varma Konduru | ||
| 245 | 0 | _aASIC implementation of five stage pipelined RISC-V processor core | |
| 260 |
_aShiv Nadar University, Dadri _bDepartment of Electrical Engineering, School of Engineering _c2025 |
||
| 300 |
_a37p. _c26cm |
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| 650 | _aEngineeringElectrical EngineeringElectronics and Communication Engineering | ||
| 700 | _aUnder supervision of Dr. Rakesh Palisetty | ||
| 942 | _cPR | ||
| 999 |
_c63944 _d63944 |
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