000			00558nam a2200133Ia 4500
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100			_aMahita Yalamanchili
245		2	_aA Hierarchically reconfigurable SRAM-based compute-in-memory macro for edge computing
260			_aShiv Nadar University, Dadri _bDepartment of Electrical Engineering, School of Engineering _c2025
300			_a28p. _c26cm
650			_aEngineeringElectrical EngineeringElectronics and Communication Engineering
700			_aUnder supervision of Dr.Subhendu Bikash Santra
942			_cPR
999			_c64537 _d64537