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Design Verification and Test of Digital VLSI Circuits: Temporal Logic: Introduction and Basic Operators / Jatindra Kumar Deka and Santosh Biswas

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Computer fileSeries: NPTEL Lecture Series. Computer Science and Engineering Temporal Logic: Introduction and Basic OperatorsPublication details: Guwahati Indian Insitiute of TechnologyDescription: Video LectureSubject(s):

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Item type	Current library	Status
NPTEL SNU	SNU LIBRARY	Available

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