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CAD for VLSI Design II

Kamakoti, V. and Balachandran, Shankar

CAD for VLSI Design II : Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis / V. Kamakoti and Shankar Balachandran - IIT Madras ; Indian Institute of Technology Madras - Chapter 10 ; 20 p. , pdf lecture - NPTEL Lecture Series , Chapter 10 : Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis .

Subjects--Topical Terms:
Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis
CAD for VLSI Design II
Computer Science & Engineering
NPTEL
V. Kamakoti and Shankar Balachandran
IIT Madras

Dewey Class. No.: 004

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