Normal view MARC view ISBD view

CAD for VLSI Design II

Kamakoti, V. and Balachandran, Shankar

CAD for VLSI Design II : Logical effort - Optimizing performance / V. Kamakoti and Shankar Balachandran - IIT Madras ; Indian Institute of Technology Madras - Chapter 19 ; 23 p. , pdf lecture - NPTEL Lecture Series , Chapter 19 : Logical Effort and Gain based Synthesis .

Subjects--Topical Terms:
Logical Effort and Gain based Synthesis
CAD for VLSI Design II
Computer Science & Engineering
NPTEL
V. Kamakoti and Shankar Balachandran
IIT Madras

Dewey Class. No.: 004

Place hold
Print
Cite
Add to your cart (remove)
Save record
BIBTEX Dublin Core MARCXML MARC (non-Unicode/MARC-8) MARC (Unicode/UTF-8) MARC (Unicode/UTF-8, Standard) MODS (XML) RIS
More searches

Search for this title in:
Other Libraries (WorldCat) Other Databases (Google Scholar) Online Stores (Bookfinder.com)