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CAD for VLSI Design II

Kamakoti, V. and Balachandran, Shankar

CAD for VLSI Design II : Logical Effort and Gain based Synthesis (Contd) / V. Kamakoti and Shankar Balachandran - IIT Madras ; Indian Institute of Technology Madras - Chapter 20 ; 22 p. , pdf lecture - NPTEL Lecture Series , Chapter 20 : Logical Effort and Gain based Synthesis (Contd) .

Subjects--Topical Terms:
Logical Effort and Gain based Synthesis (Contd)
CAD for VLSI Design II
Computer Science & Engineering
NPTEL
V. Kamakoti and Shankar Balachandran
IIT Madras

Dewey Class. No.: 004

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