Design Verification and Test of Digital VLSI Circuits:
"Biswas, Santosh" "Deka, Jatindra Kumar"
Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-3 / Jatindra Kumar Deka and Santosh Biswas - Guwahati Indian Insitiute of Technology - Video Lecture - NPTEL Lecture Series Computer Science and Engineering Two level Boolean Logic Synthesis-3 .
"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
Computer Science and Engineering
Design Verification and Test of Digital VLSI Circuits
IIT Guwahati
NPTEL
Two level Boolean Logic Synthesis-3
Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-3 / Jatindra Kumar Deka and Santosh Biswas - Guwahati Indian Insitiute of Technology - Video Lecture - NPTEL Lecture Series Computer Science and Engineering Two level Boolean Logic Synthesis-3 .
"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
Computer Science and Engineering
Design Verification and Test of Digital VLSI Circuits
IIT Guwahati
NPTEL
Two level Boolean Logic Synthesis-3
