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Design Verification and Test of Digital VLSI Circuits:

"Biswas, Santosh" "Deka, Jatindra Kumar"

Design Verification and Test of Digital VLSI Circuits: Heuristic Minimization of Two-Level Circuits / Jatindra Kumar Deka and Santosh Biswas - Guwahati Indian Insitiute of Technology - Video Lecture - NPTEL Lecture Series Computer Science and Engineering Heuristic Minimization of Two-Level Circuits .

Subjects--Topical Terms:
"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
Computer Science and Engineering
Design Verification and Test of Digital VLSI Circuits
Heuristic Minimization of Two-Level Circuits
IIT Guwahati
NPTEL

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