Normal view MARC view ISBD view

Design Verification and Test of Digital VLSI Circuits:

"Biswas, Santosh" "Deka, Jatindra Kumar"

Design Verification and Test of Digital VLSI Circuits: Scan Chain based Sequential Circuit Testing-2 / Jatindra Kumar Deka and Santosh Biswas - Guwahati Indian Insitiute of Technology - Video Lecture - NPTEL Lecture Series Computer Science and Engineering Scan Chain based Sequential Circuit Testing-2 .

Subjects--Topical Terms:
"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
Computer Science and Engineering
Design Verification and Test of Digital VLSI Circuits
IIT Guwahati
NPTEL
Scan Chain based Sequential Circuit Testing-2

Place hold
Print
Cite
Add to your cart (remove)
Save record
BIBTEX Dublin Core MARCXML MARC (non-Unicode/MARC-8) MARC (Unicode/UTF-8) MARC (Unicode/UTF-8, Standard) MODS (XML) RIS
More searches

Search for this title in:
Other Libraries (WorldCat) Other Databases (Google Scholar) Online Stores (Bookfinder.com)