100 power tips for FPGA designers (Record no. 60857)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01465nam a22002177a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20230920123209.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 230920b |||||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781461186298 |
| 028 ## - DISTRIBUTOR NAME | |
| Distributor Name | : Zafaa Book & Distributors |
| Distributor address | : 313/56F, 49A, Anand Nagar, Inderlok, Delhi. |
| Bill Number | : ZBD0148 |
| Bill Date | : 15/09/2023 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 STA |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Stavinov, Evgeni. |
| 245 ## - TITLE STATEMENT | |
| Title | 100 power tips for FPGA designers |
| Statement of responsibility, etc | / Evgeni Stavinov. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher, distributor, etc | : Evgeni Stavinov |
| Date of publication, distribution, etc | , 2011. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xii, 453p. |
| Dimensions | : 26cm. |
| 365 ## - TRADE PRICE | |
| Price amount | 4307 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book is a collection of short articles on various aspects of FPGA design: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, design methodologies, performance, area and power optimizations, RTL coding, IP core selection, and many others. The book is intended for system architects, design engineers, and students who want to improve their FPGA design skills. Both novice and seasoned logic and hardware engineers can find bits of useful information.This book is written by a practicing FPGA logic designer, and contains a lot of illustrations, code examples, and scripts. Rather than providing information applicable to all FPGA vendors, this book edition focuses on Xilinx Virtex-6 and Spartan-6 FPGA families. Code examples are written in Verilog HDL. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Field programmable gate arrays |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Field programmable |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Design and construction |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Date acquired | Source of acquisition | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | Not For Loan | SNU LIBRARY | SNU LIBRARY | 20/09/2023 | Zafaa Books | 4307.00 | 621.395 STA | 29570 | 20/09/2023 | 20/09/2023 | Books |