APA

Aditya Chechi;Prithviraj Varma Konduru, Under supervision of Dr. Rakesh Palisetty, . (2025). ASIC implementation of five stage pipelined RISC-V processor core. Shiv Nadar University, Dadri: Department of Electrical Engineering, School of Engineering.

Chicago

Aditya Chechi;Prithviraj Varma Konduru, Under supervision of Dr. Rakesh Palisetty, . 2025. ASIC implementation of five stage pipelined RISC-V processor core. Shiv Nadar University, Dadri: Department of Electrical Engineering, School of Engineering.

Harvard

Aditya Chechi;Prithviraj Varma Konduru, Under supervision of Dr. Rakesh Palisetty, . (2025). ASIC implementation of five stage pipelined RISC-V processor core. Shiv Nadar University, Dadri: Department of Electrical Engineering, School of Engineering.

MLA

Aditya Chechi;Prithviraj Varma Konduru, Under supervision of Dr. Rakesh Palisetty, . ASIC implementation of five stage pipelined RISC-V processor core. Shiv Nadar University, Dadri: Department of Electrical Engineering, School of Engineering. 2025.