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12401.
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Design Verification and Test of Digital VLSI Circuits: Multilevel Implementation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Multilevel Implementation
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Publication details: Guwahati Indian Insitiute of Technology
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12402.
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Design Verification and Test of Digital VLSI Circuits: Introduction to formal methods for design verification / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to formal methods for design verification
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Publication details: Guwahati Indian Insitiute of Technology
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12403.
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Design Verification and Test of Digital VLSI Circuits: Temporal Logic: Introduction and Basic Operators / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Temporal Logic: Introduction and Basic Operators
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Publication details: Guwahati Indian Insitiute of Technology
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12404.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL
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Publication details: Guwahati Indian Insitiute of Technology
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12405.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL � Continued / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL � Continued
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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12406.
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Design Verification and Test of Digital VLSI Circuits: Equivalence between CTL Formulas / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Equivalence between CTL Formulas
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Publication details: Guwahati Indian Insitiute of Technology
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12407.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Model Checking / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Model Checking
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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12408.
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Design Verification and Test of Digital VLSI Circuits: Model Checking Algorithms I / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking Algorithms I
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Publication details: Guwahati Indian Insitiute of Technology
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12409.
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Design Verification and Test of Digital VLSI Circuits: Model Checking Algorithms II / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking Algorithms II
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Publication details: Guwahati Indian Insitiute of Technology
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12410.
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Design Verification and Test of Digital VLSI Circuits: Model Checking with Fairness / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking with Fairness
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Publication details: Guwahati Indian Insitiute of Technology
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12411.
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Design Verification and Test of Digital VLSI Circuits: Binary Decision Diagram: Introduction and construction / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Binary Decision Diagram: Introduction and construction
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Publication details: Guwahati Indian Insitiute of Technology
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12412.
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Design Verification and Test of Digital VLSI Circuits: Ordered Binary Decision Diagram / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Ordered Binary Decision Diagram
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Publication details: Guwahati Indian Insitiute of Technology
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12413.
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Design Verification and Test of Digital VLSI Circuits: Operation on Ordered Binary Decision Diagram / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Operation on Ordered Binary Decision Diagram
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12414.
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Design Verification and Test of Digital VLSI Circuits: Ordered Binary Decision Diagram for State Transition Systems / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Ordered Binary Decision Diagram for State Transition Systems
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12415.
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Design Verification and Test of Digital VLSI Circuits: Symbolic Model Checking / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Symbolic Model Checking
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Publication details: Guwahati Indian Insitiute of Technology
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12416.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Digital VLSI Testing / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Digital VLSI Testing
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Publication details: Guwahati Indian Insitiute of Technology
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12417.
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Design Verification and Test of Digital VLSI Circuits: Functional and Structural Testing / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Functional and Structural Testing
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Publication details: Guwahati Indian Insitiute of Technology
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12418.
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Design Verification and Test of Digital VLSI Circuits: Fault Equivalence / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Equivalence
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12419.
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Design Verification and Test of Digital VLSI Circuits: Fault Simulation-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Simulation-1
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Publication details: Guwahati Indian Insitiute of Technology
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12420.
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Design Verification and Test of Digital VLSI Circuits: Fault Simulation-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Simulation-2
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Publication details: Guwahati Indian Insitiute of Technology
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