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13481.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-1
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Publication details: Guwahati Indian Insitiute of Technology
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13482.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-2
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Publication details: Guwahati Indian Insitiute of Technology
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13483.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-3 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-3
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Publication details: Guwahati Indian Insitiute of Technology
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13484.
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Design Verification and Test of Digital VLSI Circuits: Heuristic Minimization of Two-Level Circuits / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Heuristic Minimization of Two-Level Circuits
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Publication details: Guwahati Indian Insitiute of Technology
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13485.
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Design Verification and Test of Digital VLSI Circuits: Finite State Machine Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Finite State Machine Synthesis
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Publication details: Guwahati Indian Insitiute of Technology
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13486.
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Design Verification and Test of Digital VLSI Circuits: Multilevel Implementation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Multilevel Implementation
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Publication details: Guwahati Indian Insitiute of Technology
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13487.
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Design Verification and Test of Digital VLSI Circuits: Introduction to formal methods for design verification / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to formal methods for design verification
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Publication details: Guwahati Indian Insitiute of Technology
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13488.
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Design Verification and Test of Digital VLSI Circuits: Temporal Logic: Introduction and Basic Operators / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Temporal Logic: Introduction and Basic Operators
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Publication details: Guwahati Indian Insitiute of Technology
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13489.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL
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Publication details: Guwahati Indian Insitiute of Technology
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13490.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL � Continued / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL � Continued
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13491.
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Design Verification and Test of Digital VLSI Circuits: Equivalence between CTL Formulas / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Equivalence between CTL Formulas
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13492.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Model Checking / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Model Checking
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13493.
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Design Verification and Test of Digital VLSI Circuits: Model Checking Algorithms I / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking Algorithms I
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13494.
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Design Verification and Test of Digital VLSI Circuits: Model Checking Algorithms II / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking Algorithms II
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13495.
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Design Verification and Test of Digital VLSI Circuits: Model Checking with Fairness / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking with Fairness
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Publication details: Guwahati Indian Insitiute of Technology
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13496.
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Design Verification and Test of Digital VLSI Circuits: Binary Decision Diagram: Introduction and construction / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Binary Decision Diagram: Introduction and construction
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Publication details: Guwahati Indian Insitiute of Technology
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13497.
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Design Verification and Test of Digital VLSI Circuits: Ordered Binary Decision Diagram / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Ordered Binary Decision Diagram
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13498.
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Design Verification and Test of Digital VLSI Circuits: Operation on Ordered Binary Decision Diagram / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Operation on Ordered Binary Decision Diagram
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13499.
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Design Verification and Test of Digital VLSI Circuits: Ordered Binary Decision Diagram for State Transition Systems / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Ordered Binary Decision Diagram for State Transition Systems
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13500.
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Design Verification and Test of Digital VLSI Circuits: Symbolic Model Checking / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Symbolic Model Checking
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Publication details: Guwahati Indian Insitiute of Technology
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