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61.
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Design Verification and Test of Digital VLSI Circuits: Model Checking with Fairness / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking with Fairness
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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62.
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Design Verification and Test of Digital VLSI Circuits: Binary Decision Diagram: Introduction and construction / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Binary Decision Diagram: Introduction and construction
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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63.
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Design Verification and Test of Digital VLSI Circuits: Ordered Binary Decision Diagram / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Ordered Binary Decision Diagram
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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64.
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Design Verification and Test of Digital VLSI Circuits: Operation on Ordered Binary Decision Diagram / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Operation on Ordered Binary Decision Diagram
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Publication details: Guwahati Indian Insitiute of Technology
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65.
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Design Verification and Test of Digital VLSI Circuits: Ordered Binary Decision Diagram for State Transition Systems / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Ordered Binary Decision Diagram for State Transition Systems
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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66.
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Design Verification and Test of Digital VLSI Circuits: Symbolic Model Checking / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Symbolic Model Checking
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Publication details: Guwahati Indian Insitiute of Technology
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67.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Digital VLSI Testing / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Digital VLSI Testing
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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68.
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Design Verification and Test of Digital VLSI Circuits: Functional and Structural Testing / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Functional and Structural Testing
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Publication details: Guwahati Indian Insitiute of Technology
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69.
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Design Verification and Test of Digital VLSI Circuits: Fault Equivalence / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Equivalence
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Publication details: Guwahati Indian Insitiute of Technology
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70.
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Design Verification and Test of Digital VLSI Circuits: Fault Simulation-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Simulation-1
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71.
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Design Verification and Test of Digital VLSI Circuits: Fault Simulation-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Simulation-2
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Publication details: Guwahati Indian Insitiute of Technology
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72.
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Design Verification and Test of Digital VLSI Circuits: Fault Simulation-3 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Fault Simulation-3
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73.
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Design Verification and Test of Digital VLSI Circuits: Testability Measures (SCOAP) / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Testability Measures (SCOAP)
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74.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
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75.
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Design Verification and Test of Digital VLSI Circuits: D-Algorithm-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering D-Algorithm-1
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Publication details: Guwahati Indian Insitiute of Technology
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76.
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Design Verification and Test of Digital VLSI Circuits: D-Algorithm-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering D-Algorithm-2
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Publication details: Guwahati Indian Insitiute of Technology
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77.
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Design Verification and Test of Digital VLSI Circuits: ATPG for Synchronous Sequential Circuits / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering ATPG for Synchronous Sequential Circuits
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Publication details: Guwahati Indian Insitiute of Technology
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78.
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Design Verification and Test of Digital VLSI Circuits: Scan Chain based Sequential Circuit Testing-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scan Chain based Sequential Circuit Testing-1
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79.
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Design Verification and Test of Digital VLSI Circuits: Scan Chain based Sequential Circuit Testing-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scan Chain based Sequential Circuit Testing-2
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80.
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Design Verification and Test of Digital VLSI Circuits: Built in Self Test-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Built in Self Test-1
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Publication details: Guwahati Indian Insitiute of Technology
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