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CAD for VLSI Design II : Logical effort - Optimizing performance / V. Kamakoti and Shankar Balachandran by Series: NPTEL Lecture Series. , Chapter 19 : Logical Effort and Gain based Synthesis
Material type: Text Text
Publication details: IIT Madras ; Indian Institute of Technology Madras
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Availability: Items available for loan: SNU LIBRARY (1)Call number: 004.

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2.
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CAD for VLSI Design II : Logical Effort and Gain based Synthesis (Contd) / V. Kamakoti and Shankar Balachandran by Series: NPTEL Lecture Series. , Chapter 20 : Logical Effort and Gain based Synthesis (Contd)
Material type: Text Text
Publication details: IIT Madras ; Indian Institute of Technology Madras
Online resources:
Availability: Items available for loan: SNU LIBRARY (1)Call number: 004.

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