CAD for VLSI Design II : Logical effort - Optimizing performance / V. Kamakoti and Shankar Balachandran

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TextSeries: NPTEL Lecture Series. , Chapter 19 : Logical Effort and Gain based SynthesisPublication details: IIT Madras ; Indian Institute of Technology MadrasDescription: Chapter 19 ; 23 p. , pdf lectureSubject(s):

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Item type	Current library	Call number	Status	Barcode
NPTEL	SNU LIBRARY	004 (Browse shelf(Opens below))	Available	NP96

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