Design Verification and Test of Digital VLSI Circuits:
"Biswas, Santosh" "Deka, Jatindra Kumar"
Design Verification and Test of Digital VLSI Circuits: Transformations for High Level Synthesis / Jatindra Kumar Deka and Santosh Biswas - Guwahati Indian Insitiute of Technology - Video Lecture - NPTEL Lecture Series Computer Science and Engineering Transformations for High Level Synthesis .
"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
Computer Science and Engineering
Design Verification and Test of Digital VLSI Circuits
IIT Guwahati
NPTEL
Transformations for High Level Synthesis
Design Verification and Test of Digital VLSI Circuits: Transformations for High Level Synthesis / Jatindra Kumar Deka and Santosh Biswas - Guwahati Indian Insitiute of Technology - Video Lecture - NPTEL Lecture Series Computer Science and Engineering Transformations for High Level Synthesis .
"Prof. Jatindra Kumar Deka,Dr. Santosh Biswas"
Computer Science and Engineering
Design Verification and Test of Digital VLSI Circuits
IIT Guwahati
NPTEL
Transformations for High Level Synthesis
