Design Verification and Test of Digital VLSI Circuits: Transformations for High Level Synthesis / Jatindra Kumar Deka and Santosh Biswas
Material type:
Computer fileSeries: NPTEL Lecture Series. Computer Science and Engineering Transformations for High Level SynthesisPublication details: Guwahati Indian Insitiute of TechnologyDescription: Video LectureSubject(s): Online resources:
| Item type | Current library | Status | |
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NPTEL SNU
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SNU LIBRARY | Available |
Total holds: 0
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